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| 001 Behavioral Modeling - Introduction_en.vtt |
7.82Кб |
| 001 Behavioral Modeling - Introduction.mp4 |
66.98Мб |
| 001 Data flow Modeling assign statement_en.vtt |
2.27Кб |
| 001 Data flow Modeling assign statement.mp4 |
12.90Мб |
| 001 FIFO Lecture_en.vtt |
60б |
| 001 FIFO Lecture.mp4 |
1.06Мб |
| 001 FPGA_en.vtt |
14.92Кб |
| 001 FPGA.mp4 |
131.69Мб |
| 001 FSM ( Finite State Machine) & Hardware modeling of FSM, Example Verilog code_en.vtt |
22.60Кб |
| 001 FSM ( Finite State Machine) & Hardware modeling of FSM, Example Verilog code.mp4 |
126.38Мб |
| 001 Functional simulation_en.vtt |
4.63Кб |
| 001 Functional simulation.mp4 |
27.05Мб |
| 001 Functions & tasks and system tasks_en.vtt |
5.64Кб |
| 001 Functions & tasks and system tasks.mp4 |
49.68Мб |
| 001 Gate Level Model Introduction_en.vtt |
655б |
| 001 Gate Level Model Introduction.mp4 |
3.43Мб |
| 001 Hamming code complete Design & TB for error detection & correction_en.vtt |
19.53Кб |
| 001 Hamming code complete Design & TB for error detection & correction.mp4 |
213.73Мб |
| 001 Language constructs -Comments, keywords, identifier, Number specific, Operators_en.vtt |
2.24Кб |
| 001 Language constructs -Comments, keywords, identifier, Number specific, Operators.mp4 |
14.50Мб |
| 001 Memory controller with Design & TB_en.vtt |
10.00Кб |
| 001 Memory controller with Design & TB.mp4 |
92.80Мб |
| 001 Preview_en.vtt |
14.96Кб |
| 001 Preview.mp4 |
84.59Мб |
| 001 Sequence detector using FSM with complete Design & TB_en.vtt |
8.91Кб |
| 001 Sequence detector using FSM with complete Design & TB.mp4 |
65.04Мб |
| 001 Switch level modeling_en.vtt |
3.23Кб |
| 001 Switch level modeling.mp4 |
17.68Мб |
| 001 Three levels of verilog design Description_en.vtt |
3.72Кб |
| 001 Three levels of verilog design Description.mp4 |
32.95Мб |
| 001 Verilog fundamentals_en.vtt |
29.99Кб |
| 001 Verilog fundamentals.mp4 |
165.59Мб |
| 001 Verilog Program Structure -Module_en.vtt |
1.11Кб |
| 001 Verilog Program Structure -Module.mp4 |
7.39Мб |
| 001 VLSI Design flow (FPGA & ASIC)_en.vtt |
14.28Кб |
| 001 VLSI Design flow (FPGA & ASIC).mp4 |
76.54Мб |
| 002 Behavioral Modeling Constructs_en.vtt |
1.82Кб |
| 002 Behavioral Modeling Constructs.mp4 |
15.42Мб |
| 002 Datatypes - net,reg, integer, real, string, time, Parameter, Vector,Array,Memory_en.vtt |
2.98Кб |
| 002 Datatypes - net,reg, integer, real, string, time, Parameter, Vector,Array,Memory.mp4 |
17.82Мб |
| 002 Example 4x1 Mux_en.vtt |
932б |
| 002 Example 4x1 Mux.mp4 |
5.36Мб |
| 002 Example FSM - Divide by 2 clock_en.vtt |
1.94Кб |
| 002 Example FSM - Divide by 2 clock.mp4 |
11.47Мб |
| 002 Example mux_2x1 with 3 abstracts models_en.vtt |
1.84Кб |
| 002 Example mux_2x1 with 3 abstracts models.mp4 |
9.09Мб |
| 002 Example - Test bench for counter design_en.vtt |
5.36Кб |
| 002 Example - Test bench for counter design.mp4 |
62.41Мб |
| 002 File based system tasks and random generator system task_en.vtt |
7.37Кб |
| 002 File based system tasks and random generator system task.mp4 |
68.50Мб |
| 002 FPGA vs ASIC_en.vtt |
8.68Кб |
| 002 FPGA vs ASIC.mp4 |
80.12Мб |
| 002 Introduction to FIFO_en.vtt |
4.43Кб |
| 002 Introduction to FIFO.mp4 |
32.43Мб |
| 002 Operators_en.vtt |
1.90Кб |
| 002 Operators.mp4 |
17.22Мб |
| 002 Ports_en.vtt |
1.78Кб |
| 002 Ports.mp4 |
10.73Мб |
| 002 Sample program on edaplayground_en.vtt |
13.07Кб |
| 002 Sample program on edaplayground.mp4 |
87.84Мб |
| 002 Sequence detector using FSM output waveform_en.vtt |
1.20Кб |
| 002 Sequence detector using FSM output waveform.mp4 |
13.32Мб |
| 003 Arithmetic Operators_en.vtt |
1.37Кб |
| 003 Arithmetic Operators.mp4 |
8.55Мб |
| 003 Compiler Directives_en.vtt |
1.98Кб |
| 003 Compiler Directives.mp4 |
15.89Мб |
| 003 Example FSM- Divide by 3 clock_en.vtt |
2.61Кб |
| 003 Example FSM- Divide by 3 clock.mp4 |
22.53Мб |
| 003 Example Full Adder_en.vtt |
733б |
| 003 Example Full Adder.mp4 |
3.61Мб |
| 003 Example - Test bench for Pulse generator_en.vtt |
5.61Кб |
| 003 Example - Test bench for Pulse generator.mp4 |
58.28Мб |
| 003 Port Connection Rules_en.vtt |
1.90Кб |
| 003 Port Connection Rules.mp4 |
13.03Мб |
| 003 Procedural Blocks- initial & always_en.vtt |
7.63Кб |
| 003 Procedural Blocks- initial & always.mp4 |
61.08Мб |
| 003 Read file and write in to memory system task_en.vtt |
2.02Кб |
| 003 Read file and write in to memory system task.mp4 |
18.91Мб |
| 003 Write Read Operation of Normal RAM_en.vtt |
3.83Кб |
| 003 Write Read Operation of Normal RAM.mp4 |
26.95Мб |
| 004 Design Methodologies Approaches_en.vtt |
849б |
| 004 Design Methodologies Approaches.mp4 |
4.69Мб |
| 004 Example Clock Generation_en.vtt |
2.13Кб |
| 004 Example Clock Generation.mp4 |
8.37Мб |
| 004 FIFO IO (input & Outputs)_en.vtt |
1.36Кб |
| 004 FIFO IO (input & Outputs).mp4 |
8.04Мб |
| 004 Logical Operators_en.vtt |
1.65Кб |
| 004 Logical Operators.mp4 |
12.66Мб |
| 004 Programming Language Interface_en.vtt |
1.28Кб |
| 004 Programming Language Interface.mp4 |
13.49Мб |
| 004 Tri-state Buffers with Examples_en.vtt |
2.00Кб |
| 004 Tri-state Buffers with Examples.mp4 |
12.94Мб |
| 005 Array of Instance with example_en.vtt |
1.57Кб |
| 005 Array of Instance with example.mp4 |
10.72Мб |
| 005 Assignment Statements - Blocking & Non-blocking_en.vtt |
7.04Кб |
| 005 Assignment Statements - Blocking & Non-blocking.mp4 |
63.25Мб |
| 005 Block Diagram and Architecture of FIFO_en.vtt |
4.19Кб |
| 005 Block Diagram and Architecture of FIFO.mp4 |
44.46Мб |
| 005 Example Full Adder Logical operators_en.vtt |
811б |
| 005 Example Full Adder Logical operators.mp4 |
3.80Мб |
| 006 Connection of FIFO design & Test bench environment_en.vtt |
3.15Кб |
| 006 Connection of FIFO design & Test bench environment.mp4 |
18.61Мб |
| 006 Example Full Adder Arithmetic operators_en.vtt |
776б |
| 006 Example Full Adder Arithmetic operators.mp4 |
2.83Мб |
| 006 Mechanism in Non-blocking_en.vtt |
1.23Кб |
| 006 Mechanism in Non-blocking.mp4 |
4.35Мб |
| 007 Concurrency_en.vtt |
1.23Кб |
| 007 Concurrency.mp4 |
6.35Мб |
| 007 Example Binary to Gray code converter_en.vtt |
891б |
| 007 Example Binary to Gray code converter.mp4 |
4.58Мб |
| 007 Verilog HDL for FIFO design_en.vtt |
12.35Кб |
| 007 Verilog HDL for FIFO design.mp4 |
89.42Мб |
| 008 Advantage of Non-blocking assignment Example swapping_en.vtt |
1.45Кб |
| 008 Advantage of Non-blocking assignment Example swapping.mp4 |
10.20Мб |
| 008 Logical and , Logical or (&&, )_en.vtt |
1.41Кб |
| 008 Logical and , Logical or (&&, ).mp4 |
5.64Мб |
| 008 Verilog HDL code for FIFO Test Bench_en.vtt |
15.32Кб |
| 008 Verilog HDL code for FIFO Test Bench.mp4 |
147.79Мб |
| 009 Advantage of Non-blocking assignment Example Pipelining_en.vtt |
5.55Кб |
| 009 Advantage of Non-blocking assignment Example Pipelining.mp4 |
38.43Мб |
| 009 Run the simulation and finding errors and Analyze the waveform Results_en.vtt |
6.79Кб |
| 009 Run the simulation and finding errors and Analyze the waveform Results.mp4 |
61.21Мб |
| 009 Shift operators Leftright Shift_en.vtt |
2.25Кб |
| 009 Shift operators Leftright Shift.mp4 |
17.91Мб |
| 010 if-else statement Example 4x1 Mux_en.vtt |
4.35Кб |
| 010 if-else statement Example 4x1 Mux.mp4 |
30.40Мб |
| 010 Shifting without shift operator , just with concatenation operator_en.vtt |
1.28Кб |
| 010 Shifting without shift operator , just with concatenation operator.mp4 |
4.35Мб |
| 011 Case – statement Example 4x1 Mux_en.vtt |
3.63Кб |
| 011 Case – statement Example 4x1 Mux.mp4 |
34.05Мб |
| 011 Ternary operator Example 2x1 MUX, 4x1 MUX_en.vtt |
3.18Кб |
| 011 Ternary operator Example 2x1 MUX, 4x1 MUX.mp4 |
13.58Мб |
| 012 Advantage of Case over if-else_en.vtt |
1.03Кб |
| 012 Advantage of Case over if-else.mp4 |
7.98Мб |
| 012 Relational operators Example Comparator_en.vtt |
854б |
| 012 Relational operators Example Comparator.mp4 |
4.51Мб |
| 013 Equality (==) , case Equality (===) operators_en.vtt |
1.91Кб |
| 013 Equality (==) , case Equality (===) operators.mp4 |
7.13Мб |
| 013 Loops while, for, repeat, forever_en.vtt |
1.44Кб |
| 013 Loops while, for, repeat, forever.mp4 |
7.19Мб |
| 014 Parallel blocks - fork-join_en.vtt |
1.68Кб |
| 014 Parallel blocks - fork-join.mp4 |
10.79Мб |
| 014 Reduction operator Example Parity Generator_en.vtt |
1.31Кб |
| 014 Reduction operator Example Parity Generator.mp4 |
7.13Мб |
| 015 Combinational Logic Circuit Examples 8x1 Mux_en.vtt |
1.77Кб |
| 015 Combinational Logic Circuit Examples 8x1 Mux.mp4 |
7.63Мб |
| 016 Example 8x1 Mux using 4x1 mux and 2x1 mux_en.vtt |
2.60Кб |
| 016 Example 8x1 Mux using 4x1 mux and 2x1 mux.mp4 |
16.88Мб |
| 017 Example AND gate using 2x1 Mux_en.vtt |
2.06Кб |
| 017 Example AND gate using 2x1 Mux.mp4 |
5.56Мб |
| 018 Example 1x8 Demux_en.vtt |
704б |
| 018 Example 1x8 Demux.mp4 |
3.38Мб |
| 019 Example Full Adder & 4-bit Full Adder_en.vtt |
3.06Кб |
| 019 Example Full Adder & 4-bit Full Adder.mp4 |
17.04Мб |
| 020 Example 3x8 Decoder and 3x8 Decoder using 2x4 decoder_en.vtt |
1.98Кб |
| 020 Example 3x8 Decoder and 3x8 Decoder using 2x4 decoder.mp4 |
10.33Мб |
| 021 Example 8x3 encoder_en.vtt |
477б |
| 021 Example 8x3 encoder.mp4 |
2.38Мб |
| 022 Example Priority encoder_en.vtt |
1.41Кб |
| 022 Example Priority encoder.mp4 |
7.80Мб |
| 023 Example Seven Segment Display_en.vtt |
1.88Кб |
| 023 Example Seven Segment Display.mp4 |
13.39Мб |
| 024 Example ALU_en.vtt |
863б |
| 024 Example ALU.mp4 |
5.38Мб |
| 025 Sequential Logic Circuits List of Examples_en.vtt |
1.12Кб |
| 025 Sequential Logic Circuits List of Examples.mp4 |
8.07Мб |
| 026 Example D Flip Flop vs D-Latch_en.vtt |
2.13Кб |
| 026 Example D Flip Flop vs D-Latch.mp4 |
17.10Мб |
| 027 Example Synchronous Reset D-Flip flop , Asynchronous Reset D-Flip flop_en.vtt |
1.22Кб |
| 027 Example Synchronous Reset D-Flip flop , Asynchronous Reset D-Flip flop.mp4 |
4.14Мб |
| 028 Example T-Flip Flop_en.vtt |
2.24Кб |
| 028 Example T-Flip Flop.mp4 |
8.07Мб |
| 029 Example Master-slave JK Flip Flop_en.vtt |
1.26Кб |
| 029 Example Master-slave JK Flip Flop.mp4 |
6.14Мб |
| 030 Example Counter_en.vtt |
3.70Кб |
| 030 Example Counter.mp4 |
19.43Мб |
| 031 Example UPDown Counter_en.vtt |
4.15Кб |
| 031 Example UPDown Counter.mp4 |
27.37Мб |
| 032 Example clock divider using counter- Divide by 2,4,8,_en.vtt |
1.71Кб |
| 032 Example clock divider using counter- Divide by 2,4,8,.mp4 |
13.59Мб |
| 033 Example Pulse Generator Mod-3 pulse generator_en.vtt |
2.00Кб |
| 033 Example Pulse Generator Mod-3 pulse generator.mp4 |
18.87Мб |
| 034 Example Divide by 3 clock_en.vtt |
2.42Кб |
| 034 Example Divide by 3 clock.mp4 |
17.67Мб |
| 035 Example Ring Counter vs Jonson Counter_en.vtt |
1.93Кб |
| 035 Example Ring Counter vs Jonson Counter.mp4 |
11.75Мб |
| 036 Example Shift Registers SISO, SIPO, PISO,PIPO_en.vtt |
1.74Кб |
| 036 Example Shift Registers SISO, SIPO, PISO,PIPO.mp4 |
13.29Мб |
| 037 Example LFSR (Linear Feedback Shift Register)_en.vtt |
5.10Кб |
| 037 Example LFSR (Linear Feedback Shift Register).mp4 |
35.14Мб |
| 038 memory design_en.vtt |
3.78Кб |
| 038 memory design.mp4 |
27.02Мб |
| 38061230-arthm1.mp4 |
3.76Мб |
| Bonus Resources.txt |
386б |
| external-assets-links.txt |
412б |
| external-assets-links.txt |
633б |
| external-assets-links.txt |
212б |
| external-assets-links.txt |
212б |
| external-assets-links.txt |
78б |
| external-assets-links.txt |
689б |
| Get Bonus Downloads Here.url |
182б |